1. Field of the Invention
The present invention generally relates to memory control circuits and, more particularly, to a memory control circuit capable of preventing programs and data written in a memory from being damaged due to data dissipation so that a written memory content remains intact. Throughout the following description, a memory and an entirety of a control circuit associated therewith will simply referred to as a memory control circuit.
2. Description of the Related Art
An ideal electrically write-enabled and erasable non-volatile memory maintains data "1" and "0" intact for an unlimited period of time. In reality, however, data ("0" and "1") written in such a memory may undergo time-dependent alteration due to a defect in a manufacturing process or the like.
FIG. 15 shows a construction of a memory control circuit according to the related art. Referring to FIG. 15, the memory control circuit comprises a CPU 1 for performing a predetermined process, a data bus 2 for transferring data, an address bus 3 for transferring address data, an address latch signal generation circuit 4 for generating an address latch signal, an address latch 5 for latching the address data 102 from the address bus 3 in response to the address latch signal.
Referring again to FIG. 15, the memory control circuit also comprises a memory cell array 6 for storing data necessary for the CPU process, a word line decoder 7 for selecting word lines of the memory cell array 6 by decoding the address data 102 provided thereto, a selector decoder 8 for decoding the address data 102 for selection of bit lines of the memory cell array 6, a bit line selector 9 for selecting one of bit lines of the memory cell array 6 in response to the decoding by the decoder 8, and a sense amplifier 10 for reading data in the memory cell array 6.
Referring again to FIG. 15, the memory control circuit further comprises a data latch 11 for temporarily storing data 103 (write data or command data), a command latch 12 for temporarily storing command data 104, a command decoder 13 for decoding the command data 104 and outputting a decode signal 105 and a memory control signal generation circuit 14 for generating a memory control signal 106 for a write operation, a read operation and an erasure operation, in accordance with the decode signal from the command decoder 13, and outputting a clock generation request signal 107.
Referring again to FIG. 15, the memory control circuit also comprises a clock generation circuit 15 for outputting a clock signal 108 to the memory control signal generation circuit 14 in response to the clock generation request signal 107 from the memory control signal generation circuit 14, and frequency-dividing an external clock signal 109 so as to output a clock signal 110 to the CPU 1, and a write/read/erasure control circuit 16 for controlling data 111 to be written to, read from and erased in the memory cell array 6 via the sense amplifier 10. The write/read/erasure control circuit 16 outputs the data 103 from the data latch 11 to the sense amplifier 10 and delivers the data 111 read from the sense amplifier 111 to the data bus 2 as data 112.
FIG. 16 shows a memory read characteristic of the memory control circuit according to the related art. The power supply voltage of the sense amplifier 10 is plotted horizontally and the memory threshold level of a representative cell in the memory cell array 6 is plotted vertically. Referring to FIG. 16, numeral 201 indicates a threshold level of the memory that at which a read-"0" operation is ensured, 202 indicates an equilibrium point between the memory threshold level for the read-"0" operation and a memory threshold level for a read-"1" operation, 203 indicates the threshold level of the memory at which a read-"1" operation is ensured, and 204 indicates a curve connecting equilibrium points of the threshold levels of the memory at respective power supply voltages of the sense amplifier 10.
When data is read from the memory cell array 6, the memory control signal generation circuit 14 generates the memory control signal 106 in response to the decode signal 105 from the command decoder 13 and outputs the same to the write/read/erasure control circuit 16. The address latch 5 stores the address data 102 retrieved from the address bus 3 in accordance with the address latch signal 101 from the address latch signal generation circuit 4 and delivers the address data 102 to the word decoder 7 and the selector decoder 8.
A memory unit in the memory cell array 6 is selected in the form of a combination of the bit line selected by the bit line selector 9 in response to the address data 102 supplied to the selector decoder 8 and a word line determined by the word line decoder 7. The write/read/erasure control circuit 16 receives the memory control signal 106 for a read operation and commands the sense amplifier 10 to read data in a designated memory unit.
The sense amplifier 10 makes a determination as to whether the read data is "1" or "0". As shown in FIG. 16, the sense amplifier 10 reads data "0" in a cell having a high threshold level 201 and reads "1" in a cell having a low threshold level 203. The read data is transferred from the sense amplifier 10 to the write/read/erasure control circuit 16 so that the write/read/erasure control circuit 16 outputs the data 112 to the data bus 2.
If the threshold level of a memory cell is at the equilibrium point between two points at which the sense amplifier 10 reads "1" and "0", respectively, determination of the data is unstable. For this reason, a write operation and a read operation in each of the memory cells in the memory cell array 6 is controlled so that the threshold level of the memory cell is removed from the characteristic curve 204.
If the memory cell array 6 has a defect produced in the process of fabrication, the threshold level 201 of the memory cell, which causes the sense amplifier 10 to perform a read-"0" operation, may drop gradually to the threshold level 202, causing the sense amplifier to perform a read-"1" operation. Such a phenomenon is known as data dissipation. In the memory control circuit according to the related art, the sense amplifier 10 continues to perform a normal read operation in the presence of data dissipation. As a result, the wrong data 112 is output to the data bus 2, causing malfunction of peripheral devices connected to the data bus 2.
The memory cell control circuit according to the related art is not provided with means for detecting data dissipation and determining whether data read from the memory cell array 6 differs from the original data. Lack of such means may cause malfunction of the CPU 1 and the peripheral devices taking wrong data.
One approach to eliminate the above-described problem is disclosed in Japanese Laid-Open Patent Application 9-320300 "SEMICONDUCTOR MEMORY DEVICE" and Japanese Laid-Open Patent Application 8-297987 "NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE". According to these disclosures, data read at different read voltages are compared to each other so as to detect data dissipation. When data dissipation is detected, rewriting of data is performed. One disadvantage of such approaches is that, for detection of data dissipation, two data read operations are required in addition to normal data processing.